As a CPU Physical Design Timing Engineer at Qualcomm, you will define, develop, and drive CPU timing closure for Oryon CPU Cores. You will collaborate with microarchitecture and RTL design teams to develop timing constraints and implement designs that meet power, area, and performance goals. This role offers the opportunity to work with industry-leading technology nodes and engage with Qualcomm's central timing technology team. Your contributions will significantly impact multiple CPU projects and enhance your professional growth.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of relevant work experience, or a Master's degree with 3+ years, or a PhD with 2+ years.
• Strong experience in design automation using TCL, Perl, or Python.
• Familiarity with digital flow design implementation from RTL to GDS using tools like ICC and Innovus.

• Set up, converge, review, and sign off on STA for multi-mode, multi-voltage domain designs of Oryon CPU Cores.
• Conduct timing analysis, validation, and debugging across multiple PVT conditions using PT/Tempus.
• Run Primetime and/or Tempus for STA flow optimization and perform Spice to STA correlation.
• Identify root causes of timing miscorrelation at different design levels and propose solutions.
• Evaluate multiple timing methodologies and tools across different designs and technology nodes.
• Develop automation scripts within STA/PD tools for methodology development.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.