The Senior RTL Design Engineer role focuses on shaping the future of AI/ML hardware acceleration at Google. You will work with cutting-edge TPU technology that powers demanding AI applications. The position involves designing and implementing high-speed digital blocks for communication systems, contributing to the development of custom silicon solutions. You will collaborate with a team dedicated to redefining capabilities in AI and Infrastructure.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 8 years of experience in digital signal processing (DSP) design or high-speed digital logic design.
• Experience implementing digital blocks for communication systems or PHY, such as filters and timing recovery.
• Experience in MATLAB, Python, or C++.

• Design and implement high-speed blocks, taking end-to-end ownership of complex modules within the larger system.
• Solve complex implementation issues related to GHz-frequency timing closure and advanced process nodes.
• Transform high-level architectural specifications and communication theory models into efficient, bit-exact implementations.
• Perform fixed-point analysis and micro-architectural trade-offs.
• Execute and optimize the front-end design flow for assigned components to ensure sign-off quality designs.
• Collaborate closely with verification teams to develop bit-exact C++/SystemC models and ensure seamless integration.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.