The TPU PCIe RTL Design Engineer role at Google involves shaping the future of AI/ML hardware acceleration by developing custom silicon solutions for Tensor Processing Units (TPUs). The engineer will work on high-performance PCIe subsystems and foundational SoC infrastructure, collaborating closely with software and hardware teams. This position offers the opportunity to tackle challenging technical problems in a dynamic environment, contributing to innovations that power Google's AI and machine learning workloads. The role requires a strong background in ASIC design and a focus on PCIe architecture.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience in ASIC design, including one project focused on PCIe logic.
• Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
• Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
• Experience with PCIe protocol layers or LTSSM.
• Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows.

• Lead the PCIe microarchitecture and RTL development, ensuring high-performance designs that adhere to Power, Performance, and Area targets.
• Manage the full RTL lifecycle, including documentation and coding, ensuring the design is sign-off ready for Lint, CDC, and synthesis.
• Partner with system architects to integrate the PCIe subsystem, ensuring it meets chip-level bandwidth, latency, and power consumption goals.
• Coordinate with Verification and Physical Design teams to develop test plans and achieve successful timing closure.
• Resolve complex protocol issues and lead post-silicon bring-up to ensure link integrity and subsystem performance.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.