The role is for a senior physical design engineer at Intel's Neuromorphic Computing Lab, focusing on advanced semiconductor technologies and next-generation computing architectures. The team is dedicated to transforming neuromorphic computing breakthroughs into real-world products that enhance AI systems. The engineer will work on physical integration solutions and lead design closure activities to meet performance, power, and area targets. A passion for innovation and willingness to learn new methodologies is essential.

• Bachelor's degree and 6+ years or Master's degree and 4+ years of hands-on physical design experience, delivering multiple silicon tape-outs.
• 6+ years of experience in setting up floorplans, defining timing and power constraints, and iterating through synthesis, place and route to meet product KPIs.
• 6+ years of experience with scripting languages such as Perl, TCL, Python, etc.
• 4+ years of experience in debugging FEV and RV reports and planning ECOs.
• 2+ years of experience in chiplet integration and/or advanced packaging.
• 1+ year of experience using AI tools for setting up tool flows, debugging, and improving overall productivity.

• Understand system specification to drive down package and die-level requirements.
• Architect full-chip floorplans and work with designers to set up partition-level floorplans with macro/pin placements and keep-outs.
• Work with RTL designers to define timing constraints; run synthesis and place-and-route trials; fix timing, EM/IR, LVS and DRC violations.
• Run back-annotated VCS+SDF simulations and iterate on meeting power/performance targets by providing feedback to designers.
• Write custom scripts and define tool flows to manipulate synthesis and physical design tools for low power/high performance custom designs.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.