The Senior CPU RTL Design Engineer – Power Management role at Intel involves working within the CPU Design Team to architect and deliver next-generation processors with a focus on power management and energy efficiency. This position requires deep expertise in low-power CPU/SoC design and collaboration with various teams to ensure successful silicon delivery. The ideal candidate will have a strong background in RTL development and a commitment to optimizing power, performance, and area. This role is suited for engineers who can operate independently and influence design decisions.

• Bachelor's degree in Electrical/Computer Engineering, Computer Science or related field with 9+ years of relevant experience, or a Master's degree with 7+ years of experience.
• Experience with power management concepts such as DVFS, power states, and budgeting.
• Experience in low-power or power-aware CPU or SoC RTL design.
• Proficiency in RTL development using Verilog/SystemVerilog.
• Strong understanding of debug and system-level design.

• Define, design, and implement CPU microarchitecture features.
• Develop and deliver RTL for CPU IP blocks.
• Drive power, performance, and area optimization with a focus on power-aware RTL design.
• Design and validate multi-clock domain and CDC solutions.
• Contribute to CPU power management features including dynamic voltage and frequency scaling.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.