Intel is seeking a Senior Director of Engineering to lead the Physical Design organization for DDR and LPDDR Memory PHY IPs. This role involves managing a global team of over 50 engineers across various locations, focusing on delivering high-performance memory solutions. The successful candidate will drive end-to-end physical implementation and execution excellence while fostering a collaborative engineering culture. This position requires a blend of technical expertise and strong organizational leadership to meet aggressive product timelines.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related discipline with 15+ years of industry experience; Master's or PhD preferred.
• 18+ years of semiconductor design experience with significant leadership responsibility.
• Proven experience leading large-scale Physical Design organizations.
• Demonstrated success delivering high-speed PHY, SerDes, DDR, LPDDR, or other complex mixed-signal IPs into production.
• Deep expertise in advanced node implementation including Intel 18A, Intel 14A, 2nm-class technologies, or equivalent leading-edge process nodes.
• Extensive experience with timing closure, power optimization, signal integrity, reliability analysis, physical verification, and design signoff methodologies.
• Experience managing globally distributed teams across multiple geographic regions.
• Excellent communication, organizational, and people leadership skills.

• Lead and develop a global team of 50+ Physical Design engineers located across multiple geographies.
• Manage a mix of direct and matrix reporting relationships while fostering a high-performance, collaborative engineering culture.
• Drive organizational growth, talent development, succession planning, and employee engagement.
• Establish clear goals, execution strategies, and performance metrics aligned with business objectives.
• Own end-to-end Physical Design execution for DDR and LPDDR PHY IPs across multiple Intel product lines.
• Drive implementation activities including floorplanning, power planning, placement and optimization, clock distribution, timing closure, signal integrity, power integrity, physical verification, and design signoff.
• Lead delivery of high-speed PHY implementations targeting industry-leading performance, power, area, and reliability metrics.
• Drive predictable execution across multiple concurrent programs supporting Client, Datacenter, and ASIC/Foundry products.
• Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product Engineering, and Technology Development teams.
• Manage schedule, resource allocation, risk mitigation, and milestone delivery.
• Champion next-generation Physical Design methodologies, automation, and AI-assisted design flows.
• Drive productivity improvements through scalable automation and design reuse strategies.
• Promote technical innovation, patents, and continuous improvement initiatives.
• Communicate effectively with senior engineering leaders, product teams, and executive management.
• Drive alignment across geographically distributed organizations and external partners.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.