The Senior Test Engineer for CMOS Backplane at Raxium, part of Google, focuses on developing and optimizing test solutions for microLED display panels. This role involves working closely with design engineers to ensure hardware meets quality and reliability standards. The position is part of a team that aims to innovate in the display technology sector, leveraging advanced semiconductor materials. Candidates will engage in both research and development as well as production environments.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field.
• 4 years of experience with Silicon, CMOS, and IC test development.
• 3 years of experience with Silicon test hardware, software debugging, and data analysis in an R&D or manufacturing environment.
• Master's degree or PhD in a related field is preferred.
• Experience with testing software development, Python, and SQL databases.

• Develop, validate, and optimize CMOS Backplane test solutions for microLED display panels.
• Interface with wafer-level probe cards and test equipment for CMOS/Silicon testing.
• Identify and resolve electrical issues during wafer-level testing using various testing equipment.
• Collaborate with engineering teams to implement high-speed automated testing solutions.
• Enhance and develop test frameworks based on requirements from the Reliability Team.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.