The Senior Design Engineer, RTL role at Google involves developing custom silicon solutions that enhance the performance of Google's direct-to-consumer products. The position requires collaboration with multi-disciplinary teams to innovate hardware experiences that are efficient and powerful. The engineer will leverage their expertise in ASIC development to define microarchitecture specifications and integrate intellectual property blocks into complex designs. This role is crucial for shaping the future of hardware technology at Google.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with IP Development or Integration.
• Experience in ASIC development with Verilog or VHDL.

• Define the detailed microarchitecture specifications for silicon subsystems and small to medium-sized intellectual property blocks to meet performance, area, and power requirements.
• Integrate internal and external intellectual property blocks seamlessly into complex silicon designs and multi-component subsystems.
• Execute production-grade RTL coding, debug intricate function and performance simulation issues, and conduct standard lint, clock domain crossing, formal verification, and unified power format checks.
• Partner closely with validation teams during test plan formulation and coverage analysis for comprehensive subsystem and chip-level design verification.
• Drive technical alignment across multi-disciplinary and multi-site engineering groups to resolve architectural issues and ensure successful product delivery.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.