AMD is seeking a Senior Silicon Design Engineer to develop and maintain block-level RTL IP and MP subsystems. The role involves debugging RTL designs and achieving design feature closure while collaborating with various teams. The engineer will provide technical leadership in IP functionality and design methodology development. This position is crucial for advancing AMD's technology in supercomputing and AI.

• Master's degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, or a related field.
• One year of experience in the job offered or a closely related engineering role.
• Experience in hardware verification.
• Knowledge of logic and circuit design.
• Familiarity with CAD tools.
• Understanding of SOC or system architecture.
• Proficiency in RTL design or coding.
• Experience with Verilog or VHDL.
• Knowledge of ASIC design tools including synthesis, simulation, equivalence checking, and static timing analysis.
• Experience with Front-End EDA tools.
• Proficiency in C++ and Python.
• Understanding of object-oriented design and data structures.

• Develop and maintain block-level RTL IP and MP subsystems' feature specifications and micro-architecture.
• Debug RTL designs using C-DPI directed test methodology and verification team’s testbenches.
• Achieve design feature closure by analyzing coverage metrics.
• Triage retrogressions and debug specific simulations.
• Work with design, verification, and other teams to resolve technical issues.
• Participate in verification testbench and test plan specification.
• Influence testbench architecture development with a focus on design for verification.
• Review and improve feature and coverage test plans.
• Debug and resolve integration issues with SoC Integration, SoC DV, and post-silicon validation teams.
• Provide technical leadership in IP functionality and design methodology development.

• AMD provides a competitive 'Total Rewards' package that focuses on financial growth, health, and work-life balance.