JobsSr. Manager Silicon Design Engineering
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Sr. Manager Silicon Design Engineering

AMD

Location

Santa Clara, CA

Type

Full-time

Posted

8/18/2026

Compensation

USD $187,600.00/Yr. – USD $268,000.00/Yr.

Undergraduate with 5+ Years of Experience
Approval 98.6%·Filings 728·New hires 184·
Established Sponsor
·FY 2025

Job description

AMD is seeking a Senior Manager of Silicon Design Engineering to develop and establish timing closure methodologies for SoC and IP blocks. This role involves overseeing STA closure for complex designs and collaborating with various teams to address technical challenges. The ideal candidate will leverage their extensive knowledge in physical design and full-chip timing to ensure high-quality, on-time delivery of cutting-edge designs. The position also includes responsibilities for architectural analysis and managing silicon design projects.

Requirements

  • Master's degree or foreign equivalent in Electronics Engineering, Computer Science, Computer Engineering, or Electrical Engineering or related field.
  • Four years of experience in the job offered or a closely related engineering role.
  • Alternatively, a Bachelor's degree or foreign equivalent in the same fields and six years of experience in the job offered or a closely related engineering role.
  • Experience using Computer-Aided Design (CAD) tools to oversee the entire chip design process.
  • Experience overseeing the physical design of deep submicron digital ASICs.
  • Experience with ASIC design tools, including synthesis, simulation, equivalence checking, and static timing analysis.
  • Experience using back-end Electronic Design Automation (EDA) tools for chip design implementation.
  • Scripting experience in TCL, Perl, or Python for automating design processes.
  • Experience overseeing Static Timing Analysis (STA) closure.
  • Experience managing silicon design projects and leading an engineering team.

Responsibilities

  • Develop and establish timing closure methodologies and strategies for SoC and IP blocks.
  • Oversee STA closure for complex SoC designs featuring chiplet and 3D stack interfaces.
  • Collaborate cross-functionally with IP, Domain, CAD, and Methodology teams to identify and address technical challenges.
  • Take responsibility for architectural analysis and the scoping/assessment of feature changes.
  • Partner closely with design teams to refine clocking, area, and floorplan.
  • Assist Post-Silicon teams with debugging and resolving timing issues.
  • Utilize knowledge of engineering principles and design techniques to contribute to product development.

Benefits

  • AMD provides a competitive 'Total Rewards' package that focuses on financial growth, health, and work-life balance.

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