Qualcomm Technologies, Inc. is seeking a Senior ASIC Design Engineer to join their Next Generation, High-Speed Memory and Cache Controller team. This role focuses on the design and deployment of high-speed memory subsystems, including HBM, LPDDR, and DDR technologies. The engineer will work closely with various system components such as CPUs and GPUs to enable high-speed designs. Responsibilities include architecture development, RTL coding, and collaboration with verification engineers to ensure high-quality designs.

• Bachelor's or Master's degree in Science, Engineering, or a related field.
• 5+ years of ASIC design, RTL coding, and front-end digital design experience.
• 3+ years of Hardware Architecture experience.
• Experience with LPDDR memory and cache controllers.
• Exposure to HBM memory type designs.

• Develop architecture and design specifications for high-speed memory subsystems.
• Implement and deliver RTL designs while collaborating with verification engineers.
• Debug designs and provide support during integration into the chip.
• Conduct synthesis, timing closure, and power analysis tasks.
• Contribute to improvements in design methodology to enhance productivity and quality.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.