The role involves leading and planning the implementation of complex ASIC designs while utilizing advanced tools and methodologies. The individual will focus on resolving implementation challenges and optimizing design performance in a collaborative team environment. This position requires a strong understanding of digital design and verification processes, along with the ability to mentor junior engineers. The candidate will also be responsible for maintaining communication with team members to ensure alignment with project goals.

• Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Two years of experience in a related occupation.
• Proficiency in tools such as Cadence Innovus and Synopsys PTSI.
• Experience with deep sub-micron technology nodes (4nm, 3nm).

• Lead the planning and implementation of ASIC designs with ambiguous requirements.
• Develop and implement strategies for multiple IPs while reviewing junior team members' work.
• Optimize clock latencies and perform advanced power checks to meet design specifications.
• Write and review technical documentation in accordance with established templates.
• Act as a tech lead on projects and ensure team deliverables align with the execution plan.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.