This role at Qualcomm Atheros, Inc. involves independently planning and executing the digital architecture, design, Verilog RTL coding, and verification of next generation wireless and wired ASICs. The position focuses on delivering complex ASICs from functional specifications to final products while ensuring adherence to performance and power goals. The engineer will work closely with cross-functional teams to integrate subsystems into System on Chips (SoCs) for mobile applications. This position also includes responsibilities in high-speed digital and mixed-signal board design and debugging.

• Master's Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field
• Experience in digital architecture and design of ASICs
• Proficiency in Verilog RTL coding and implementation
• Knowledge of high-speed digital and mixed signal board design

• Plan and perform digital architecture and design for ASICs
• Investigate solutions for concept designs and evaluate architecture proposals
• Support design engineers with complex tests and component evaluations
• Perform circuit level debugging and provide feedback to design engineers
• Collaborate with cross-functional teams for verification and validation of subsystems

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.