Qualcomm is looking for a Design Verification Engineer to join its memory subsystem verification team. The role focuses on developing and executing verification strategies for complex digital designs, particularly memory controllers and custom memory interfaces. The successful candidate will engage in the complete verification lifecycle, from understanding design specifications to debugging failures. Strong hands-on experience with Verilog, SystemVerilog, and UVM is essential, along with an interest in memory technologies.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 3–10 years of experience in ASIC, SoC, IP, or subsystem design verification.
• Strong hands-on experience with Verilog, SystemVerilog, UVM, and SystemVerilog Assertions.
• Experience developing and debugging reusable UVM-based verification environments.
• Strong understanding of digital design and verification fundamentals.

• Develop verification strategies, test plans, and coverage plans for complex RTL designs.
• Build, enhance, and maintain reusable SystemVerilog/UVM and formal verification environments.
• Create and execute constrained-random, directed, error-injection, and corner-case tests.
• Write and maintain SystemVerilog Assertions for protocol, interface, timing, and functional verification.
• Analyze simulation failures using waveform viewers, simulation logs, and other debug tools.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.