The Senior ASIC Design Verification Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration, specifically through the development of custom silicon solutions like TPUs. The engineer will work within a team dedicated to verifying complex digital designs and ensuring the functionality of ASICs used in data centers. This position involves engaging in project definition, design verification, and silicon bring-up, contributing to innovations that impact millions of users worldwide. The AI and Infrastructure team aims to deliver unparalleled computing power and insights to Google customers.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with design verification.
• Experience in verifying digital logic at RTL using SystemVerilog/UVM for ASICs.

• Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.