The role at Qualcomm Technologies, Inc. focuses on ASIC design and physical implementation, requiring a strong understanding of synthesis, place and route, and timing/power signoff. The candidate will work within the Engineering Group, specifically in ASICS Engineering, to drive end-to-end PPA optimization. The position demands hands-on experience with advanced technology nodes and a solid grasp of low-power design methodologies. The ideal candidate will contribute to aggressive area recovery and performance pushes while ensuring timing closure across multi-clock domain designs.

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design experience, or a Master's degree with 3+ years, or a PhD with 2+ years.
• 6+ years of ASIC design, verification, validation, or integration experience is preferred.
• 2+ years of experience with architecture and design tools.
• 2+ years of experience with scripting tools and programming languages.
• 2+ years of experience with design verification methods.
• 1+ year of experience interacting with senior leadership.

• Drive PPA activities focusing on area recovery, power reduction, and performance optimization.
• Ensure timing closure for multi-clock domain and multi-corner multi-mode designs.
• Write and tune timing constraints for synthesis and physical closure.
• Utilize industry-standard tools for synthesis and PnR to optimize design.
• Implement low-power design techniques using UPF and other methodologies.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.