The Senior Power Integrity Methodology CAD Engineer at NVIDIA will focus on developing physical design methodologies for rail analysis and signoff. This role involves creating innovative solutions for IR analysis and signoff essential for NVIDIA chips. The engineer will craft workflows and tool methodologies for power and noise analysis across various projects. Joining this team means being part of a diverse and supportive environment that values collaboration and creativity.

• Master's degree or equivalent experience in Electrical Engineering or a related field.
• Minimum 10+ years of experience in EMIR flow methodology development and support.
• Strong understanding of all aspects of EMIR analysis and signoff.
• Familiarity with hierarchical design approach and hierarchical signoff.
• Experience with shift-left methodologies for EMIR optimization and convergence earlier in the chip build cycle.
• Proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++.

• Develop physical design methodologies for rail analysis and signoff.
• Come up with unique and creative solutions for pioneering IR analysis and signoff needed for NVIDIA chips.
• Craft workflows and tool methodologies for power and noise analysis across multiple projects.

• Employees at NVIDIA are often offered comprehensive, day-one benefits—including medical, dental, and vision coverage with HSA support, life and disability insurance, an Employee Assistance Program, and a 401(k) with auto-enrollment. Many roles also have generous time off and holidays, donation matching (up to $10,000), and a wide menu of extras like FSAs, commuter benefits, legal and identity-theft protection, pet insurance, and wellness discounts. Optional programs can include student-loan and home-purchase support, plus family care resources and expert medical services.