This role is for a design verification engineer at Apple, focusing on producing fully functional first silicon for IP designs. The engineer will work within a diverse team to develop verification methodologies and ensure bug-free silicon for parts of the SoC/IP. This position involves all phases of pre-silicon verification, including test-plan development and verification environment creation. The engineer will also leverage LLM technologies to enhance efficiency and quality in their work.

• BS degree in a technical subject area
• A minimum of 10 years of relevant industry experience
• Deep knowledge of OOP, SystemVerilog, and UVM
• Strong experience with verification methodologies and tools such as simulators and waveform viewers
• Excellent knowledge of one of the scripting languages such as Python, Perl, or TCL

• Establish DV methodology and develop test plans for verification.
• Develop verification environments, including stimulus, checkers, and assertions.
• Execute verification plans and debug test failures.
• Track and report DV progress using various metrics, including bugs and coverage.
• Develop scalable and portable test-benches for the IP.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.