This role is for a design verification engineer at Apple, focusing on producing fully functional first silicon for IP designs. The engineer will work within a diverse team to develop verification methodologies and environments that ensure high-quality products. Responsibilities include establishing DV methodology, developing test plans, and executing verification plans. The position requires a mindset geared towards problem-solving and innovation in verification processes.

• BS degree in a technical subject area
• Minimum 10 years of relevant industry experience
• Deep knowledge of OOP, SystemVerilog, and UVM
• Strong experience with verification methodologies and tools
• Excellent knowledge of one of the scripting languages such as Python, Perl, or TCL

• Establish DV methodology and develop test plans for verification.
• Develop verification environments including stimulus, checkers, and assertions.
• Execute verification plans and debug test failures.
• Develop detailed test and coverage plans based on micro-architecture.
• Track and report DV progress using various metrics.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.