The Package Design Engineer will be part of the Silicon Integration team at Google, focusing on developing advanced package substrate designs for machine learning chips. This role involves collaborating with various engineering teams to optimize designs for performance, reliability, and assembly. The engineer will manage the entire design process, ensuring that all phases are executed efficiently. This position is crucial for integrating advanced packaging technologies into Google's chip product design pipeline.

• Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, or a related field, or equivalent practical experience.
• 8 years of experience in chip package substrate design using Cadence APD or Mentor Expedition.
• Experience in chip package substrate layout, design verification, DFM, and taping out for production.
• Experience in design automation and scripting.

• Develop physical package substrate designs for large form-factor packages for high-performance computers.
• Implement methodology and CAD flow for efficient substrate design and enhanced productivity.
• Manage co-design initiatives across chip, package, and system levels, including securing production sign-off for package designs.
• Collaborate with signal integrity/power integrity, thermal, and mechanical engineering teams to optimize product package designs.
• Define and document the requirements for the package substrate design and bill of materials.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.