The Senior ASIC Verification Engineer at AMD will play a crucial role in developing cutting-edge FPGA and ASIC technologies for various customers. This position is part of the front-end design and integration team, collaborating closely with architecture, IP design, and product engineers to ensure successful silicon outcomes. The ideal candidate will have a strong passion for digital design and verification, along with excellent communication skills to work with teams across different locations. The focus will be on verifying PCIe CXL based IPs and ensuring high design quality through rigorous testing and debugging.

• Experience with PCIe, CXL, NVMe, or ethernet protocols is essential.
• Proficiency in IP level ASIC verification is required.
• Expertise in Verilog, System Verilog, and Object Oriented programming is necessary.
• Experience in developing UVM based verification frameworks and testbenches is expected.
• Strong communication skills and the ability to work independently and in a cross-site team environment are important.

• Collaborate with architects, hardware engineers, and firmware engineers to understand new features for verification.
• Develop test plan documentation that accounts for interactions with hardware, firmware, and software driver use cases.
• Code IP or SS level UVM based testbenches and verification components such as monitors and checkers.
• Build directed and random verification tests to ensure design quality.
• Run regressions and debug test failures to maintain high functional and performance standards.

• AMD provides a competitive 'Total Rewards' package that focuses on financial growth, health, and work-life balance.