JobsTD Memory Quality and Reliability Engineer
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TD Memory Quality and Reliability Engineer

Intel

Location

Folsom, CA, Santa Clara, CA, Hillsboro, OR

Type

Full-time

Posted

9/2/2026

Compensation

$155,520 - $219,550 per year

PhD Entry-Level
Master's with 5+ Years of Experience
H-1B FY202694.2% approval-88% YoY
💎 Strong sponsor

Job description

The Memory Quality and Reliability Engineer will focus on post-silicon memory characterization, certification, and technology readiness for advanced memory technologies such as SRAM and Register File. This role involves improving certification methodologies and analyzing large-scale silicon characterization data to guide technology development and product deployment. The engineer will collaborate with various teams to transform silicon learning into actionable technology improvements. The position requires strong analytical skills and the ability to communicate complex technical findings effectively.

Requirements

  • Ph.D. in Electrical Engineering, Computer Engineering, Physics or related discipline with 2+ years of semiconductor industry experience OR M.S. in Electrical Engineering, Computer Engineering, Physics, Materials Science, or related discipline with 6+ years of semiconductor industry experience.
  • 2+ years of hands-on experience with memory testing.
  • 2+ years of experience performing quantitative analysis of large-scale memory or semiconductor datasets using statistical methods.
  • 2+ years of hands-on experience using JMP and Python for data analysis.

Responsibilities

  • Plan and execute SRAM, RF, and/or Fuse technology certification supporting technology development and certification milestones.
  • Define and maintain certification methodologies and criteria, test strategies, and readiness requirements for memory array.
  • Drive memory array characterization across multiple operating conditions to evaluate Vmin, Vmax, aging behavior, variability, and design margins.
  • Analyze silicon characterization data to identify performance gaps, failure signatures, systematic trends, and technology risks.
  • Develop, validate, and maintain silicon-based Vccmin and Vmax predictive models used for technology certification.
  • Perform silicon-to-simulation correlation assessments and drive understanding of discrepancies between measured silicon behavior and design predictions.
  • Collaborate with Yield, Design, Device Engineering, PDE, Defect Rel and FIFA teams to define root-cause hypotheses and technology improvement recommendations.
  • Generate certification reports, readiness assessments, and risk projections that support technology deployment decisions.
  • Present technical findings and recommendations to engineering leadership, program teams, and customers.
  • Drive continuous improvement of memory certification methodologies, modeling approaches, characterization flows, and data analytics infrastructure.

Benefits

  • Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.

H-1B filing history

Public USCIS petition and DOL LCA counts · latest USCIS FY2026, LCA FY2026

Filing entity: Intel Corp

As of Aug 23, 2026

Initial approvals

74

FY2026

Approval rate

94.2%

FY2026

LCA certified

2,201

FY2026

Entry-level share

0.1%

FY2026

Initial approvals YoY

-88%

Trend

LCA certified YoY

-54%

Trend

Initial approvals by fiscal year

Approval rate by fiscal year

Continuing vs initial approvals

LCA certified positions by quarter

LCA certified positions by fiscal year

Based on public USCIS and DOL filings; not a sponsorship guarantee.

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