The Senior ASIC Design Engineer will join the Next Generation, High-Speed Memory and Cache Controller Design Team at Qualcomm. This role focuses on the design and development of high-speed HBM/LPDDR/DDR memory controllers that interface with various system components. The engineer will be responsible for architecture, RTL coding, and deployment of memory systems into QCT products. Key tasks include debugging designs and contributing to design methodology improvements.

• Bachelor's or Master's degree in Science, Engineering, or related field.
• 4+ years of ASIC design, verification, validation, integration, or related work experience for Bachelor's degree holders.
• 3+ years of ASIC design, verification, validation, integration, or related work experience for Master's degree holders.
• 2+ years of ASIC design, verification, validation, integration, or related work experience for PhD holders.
• 5+ years of ASIC design, RTL coding, and front-end digital design experience.
• 3+ years of direct Hardware Architecture experience.

• Work on architecture, design (RTL coding), and deployment of high-speed memory systems.
• Develop or contribute to architecture and design specifications.
• Drive the micro-architecture of portions of the logic design.
• Implement and deliver RTL and collaborate with verification engineers.
• Debug designs and provide support when integrated into the rest of the chip.
• Perform synthesis, timing closure, physical design support, gate level simulations, and power analysis.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.