In this role at Qualcomm, you will contribute to a Python-based random test generation framework that is essential for RISC-V CPU design verification. You will work on implementing new generation objects and enhancing the assembler library to ensure bit-level correctness against the RISC-V ISA specification. The position involves collaboration with ISS and RTL verification engineers to address failures and improve RTL coverage. This is an opportunity to engage in cutting-edge CPU design verification and contribute to innovative technology.

• 2–5 years of experience in CPU design verification, ISS development, or hardware-software co-design.
• Solid Python 3 skills with comfort in generator-based coroutines and object-oriented design patterns.
• Working knowledge of the RISC-V ISA, including instruction encoding formats and privilege levels.
• Familiarity with virtual memory, PMP, and trap/interrupt handling.
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of relevant work experience, or a Master's degree with 3+ years, or a PhD with 2+ years.

• Implement new generation objects for RISC-V extensions and complex data/control-flow composable idioms.
• Add instruction forms and encodings to the Python companion assembler and verify bit-level correctness.
• Write and tune generation themes to improve RTL coverage.
• Work within the privileged-software stack including exception/interrupt handlers and page-table builders.
• Collaborate with ISS and RTL verification engineers to triage failures and adjust constraint logic.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.