This role at Apple involves developing and implementing Design For Test (DFT) architecture while collaborating with designers and verification teams. The focus is on coding Verilog RTL for DFT logic and ensuring integration with various checks. The position requires a strong understanding of timing analysis, power issues, and silicon diagnosis. This is an opportunity to work in a dynamic environment where innovation is key.

• Master's degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.
• 2 years of experience in the job offered or related occupation.
• Experience in designing and verifying RTL using Verilog hardware description language.
• Knowledge of MBIST, march algorithms, and memory fault models.
• Experience in designing Joint Test Action Group (JTAG) architecture and programming DFT control registers.
• Proficiency in automating DFT design flows using Python or Perl scripting languages.
• Knowledge of Static Timing Analysis (STA) for timing analysis.
• Experience running RTL and gate-level simulations using industry-standard tools such as VCS or NCSIM.
• Utilization of Automatic Test Pattern Generation (ATPG) tools for scan pattern generation and fault coverage analysis.
• Experience in performing silicon failure diagnosis and analysis from Automated Test Equipment (ATE).
• Knowledge of low-power design techniques to reduce overall chip power consumption.

• Develop and implement DFT architecture and document DFT specifications.
• Implement DFT infrastructure and code Verilog RTL for DFT logic.
• Collaborate with designers to integrate DFT implementations and run various checks.
• Partner with designers on STA, physical, power, and logical issues.
• Coordinate with the Design Verification team to verify DFT implementations in RTL and gate level.
• Review verification coverage and implement Engineering Change Orders (ECOs).
• Generate ATPG structural test vectors and analyze and improve test coverage.
• Engage with test engineers to debug and bring up test vectors on silicon.
• Support Test time Reduction (TTR) and silicon diagnosis efforts.
• Handle schedules and support multi-functional engineering efforts.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.