In this role as a CPU Physical Design Timing Engineer at Qualcomm, you will define, develop, and drive CPU timing closure for Oryon CPU Cores. You will collaborate with microarchitecture and RTL design teams to develop timing constraints and implement designs that meet power, area, and performance goals. The position offers opportunities for professional growth while working on cutting-edge technology nodes. You will also engage with the central timing technology team to achieve CPU performance, power, and area goals.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of relevant experience, or a Master's degree with 5+ years, or a PhD with 4+ years.
• Excellent automation skills using TCL, Perl, or Python.
• Experience in developing automation scripts for CPU STA signoff flow and methodology.
• Strong expertise in STA timing analysis basics and concepts such as AOCV/POCV.

• Set up, converge, review, and sign off on multi-mode, multi-voltage domain designs of Oryon CPU Cores.
• Conduct timing analysis, validation, and debugging across multiple PVT conditions using PT/Tempus.
• Run Primetime and/or Tempus for STA flow optimization and perform Spice to STA correlation.
• Identify the root cause of timing miscorrelation at different design levels and propose solutions.
• Evaluate multiple timing methodologies and tools on various designs and technology nodes.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.