This role involves joining a team at AMD that develops next-generation graphics and compute technologies. The candidate will work closely with various teams including Architecture, IP Design, Physical Design, and Product Engineering. The main focus is on delivering high-quality silicon and achieving first-pass silicon success. The ideal candidate will be detail-oriented and possess strong communication and problem-solving skills.

• Understanding of Design-for-Test (DFT) methodologies and DFT verification experience.
• Experience with Mentor TestKompress and/or Synopsys TetraMAX/DFTMAX.
• Experience with VCS simulation tools, Perl and Shell scripting, and Verilog RTL design.
• Bachelor's or master's degree in computer engineering, Electrical Engineering, or a related field.

• Implement and verify DFT architecture and features.
• Perform scan insertion and ATPG pattern generation.
• Verify ATPG patterns using gate-level simulation.
• Conduct test coverage and test cost reduction analysis.
• Provide post-silicon support to ensure successful bring-up and accelerate yield learning.

• AMD provides a competitive 'Total Rewards' package that focuses on financial growth, health, and work-life balance.