The Physical Design Engineer role focuses on FullChip/ASIC implementation at Google. The team is dedicated to developing custom silicon solutions that enhance Google's consumer products. This position involves driving progress in physical design and mentoring junior team members. The engineer will contribute to high-performance designs that prioritize efficiency and integration.

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 4 years of experience in physical design.
• Experience in one or more synthesis/PnR tools such as Genus, Innovus, DC, or ICC.
• Experience in high-performance synthesis, PnR, sign-off convergence, including STA and sign-off optimizations.

• Develop all aspects of ASIC RTL2GDS implementation for high Performance, Power, Area (PPA) designs.
• Manage full-chip level physical implementation.
• Define and implement innovative schemes to improve performance and power.
• Work with cross-functional teams to deliver the best quality of results.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.