This position is focused on developing and defining integrated front-end and back-end process flows for new technology nodes within Intel's Logic Technology Development team. The role requires collaboration across various teams to optimize performance and establish process windows. Candidates will analyze yield loss and perform root cause analysis to drive improvements. The environment is dynamic and supports innovation in semiconductor technology.

• PhD in Electrical Engineering, Physics, Applied Physics, Materials Science, Chemical Engineering, Mechanical Engineering, Chemistry, Optics, or a closely related semiconductor field of study.
• Hands-on cleanroom experience in interconnect process development, advanced interconnect metallization, or electrical characterization of interconnect stacks.

• Develop and define integrated front-end and back-end process flows for new technology nodes.
• Coordinate across lithography, etch, deposition, diffusion, wet clean, CMP, dielectric, and metrology teams.
• Optimize RC (resistance-capacitance) performance.
• Establish process windows and integration schemes.
• Analyze yield loss and parametric failures.
• Perform root cause analysis using statistical tools such as SPC, DOE, and FMEA.
• Drive corrective actions to improve yield and cycle time.
• Implement control plans and process monitoring strategies.
• Use statistical tools such as Cpk / Ppk, control charts, and capability analysis.
• Ensure margins for electromigration, stress migration, TDDB, and time dependent via degradation.
• Evaluate the impact of process window shifts on reliability.
• Support ramp from R&D to high-volume manufacturing (HVM).
• Document process specifications and standard operating procedures (SOPs).

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.