The ASIC Design Verification Engineer for Digital Signal Processing at Google will focus on shaping the future of AI/ML hardware acceleration. This role involves driving the verification strategy for high-speed Physical Layer digital blocks and verifying complex DSP algorithms. The engineer will work within a team that develops custom silicon solutions, specifically targeting TPU architecture integration within AI/ML systems. This position requires a strong foundation in communication theory and mixed-signal co-simulation.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 8 years of experience in design verification with a focus on digital signal processing, communication systems, or arithmetic logic blocks.
• Experience with scripting in Python, Perl, or Makefile for automation.

• Verify RTL implementations against high-level architectural reference models using bit-exact and fixed-point verification methodologies.
• Verify the stability, tracking capability, and convergence of adaptive equalization loops and timing recovery systems under varying channel impairments.
• Model and verify the functional interface between Digital DSP blocks and the Analog Front End using Real Number Modeling or SystemVerilog-AMS.
• Design, implement, and maintain scalable UVM-based simulation environments, SystemVerilog Assertions, and functional coverage metrics for digital signal processing blocks.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.