The Senior Design Verification Engineer will be part of a team focused on developing custom silicon solutions that enhance Google's consumer products. This role involves collaborating with designers and architects to create detailed test plans and ensure the functionality of multimedia design blocks. The engineer will leverage their expertise in verification methodologies to drive innovation and improve verification processes. This position is critical in shaping the next generation of hardware experiences that deliver exceptional performance and efficiency.

• Bachelor's degree in electrical engineering or computer science, or equivalent practical experience.
• 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
• Experience with interconnect protocols including AXI, APB, and ACE.
• Experience developing and maintaining verification testbenches, test cases, and test environments.

• Work with designers, architects, and other stakeholders to develop detailed test plans and deliverables.
• Plan the verification of multimedia design blocks at the subsystem level by understanding design specifications.
• Collaborate with architecture, software, design, and back-end implementation stakeholders to make technical decisions.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM.
• Identify verification gaps and demonstrate progress towards tape-out through comprehensive coverage metrics.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.