Job description
This role at Apple involves integrating internal and external intellectual property while designing system bus and control bus logic for connectivity of IP blocks to the main SOC infrastructure. The position requires collaboration with various teams, including Chip Architecture and Design Verification, to ensure successful tape-out of designs. The focus is on optimizing memories and hard macros, as well as maintaining high-quality design methodologies. The ideal candidate will have a strong background in electrical engineering and experience in low power design concepts.
Requirements
- Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
- Experience using System Verilog or Verilog to write RTL for integration components.
- Knowledge of utilizing multiple clock domains and reset domains.
- Experience with low power design concepts such as clock gating and power gating.
- Familiarity with synthesis tools from Synopsys or Cadence.
Responsibilities
- Integrate and optimize memories and hard macros required for the block.
- Run synthesis, netlist generation, and timing closure for the block.
- Develop and maintain methodology, flows, and checks for owned designs.
- Work closely with multi-disciplinary groups to ensure designs are delivered on time.
- Incorporate proper checks at every stage of the design process.
Benefits
- Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.
H-1B filing history
Public USCIS petition and DOL LCA counts · latest USCIS FY2026, LCA FY2026
Filing entity: Apple Inc
As of Aug 23, 2026
Initial approvals
1,065
FY2026
Approval rate
99.0%
FY2026
LCA certified
9,221
FY2026
Entry-level share
5.6%
FY2026
Initial approvals YoY
+30%
Trend
LCA certified YoY
-35%
Trend
Initial approvals by fiscal year
Approval rate by fiscal year
Continuing vs initial approvals
LCA certified positions by quarter
LCA certified positions by fiscal year
Based on public USCIS and DOL filings; not a sponsorship guarantee.
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