The RTL Design Engineer for TPU at Google will work on shaping the future of AI and ML hardware acceleration. This role involves designing RTL Intellectual Property (IP) for management and control subsystems within Tensor Processing Units (TPUs). The engineer will collaborate with cross-functional teams, including software and system hardware counterparts, to develop custom silicon solutions. This position offers the opportunity to contribute to innovative products that power Google's AI/ML applications.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience with scripting languages.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science is preferred.
• 8 years of experience in ASIC design.
• Experience interacting with software, system hardware, and other cross-functional teams.
• Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines and bus protocols.

• Create and review management and control subsystem's design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Evaluate features and their impact in collaboration with architecture and power teams.
• Create test plans to verify and debug design RTL with design validation teams.
• Ensure design meets physical requirements and timing closure with physical design teams.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.