The TPU RTL Design Engineer will work on shaping the future of AI and machine learning hardware acceleration at Google. This role involves designing and developing core components of Tensor Processing Units (TPUs) that power Google's AI/ML applications. The engineer will focus on creating high-speed interconnect subsystems and collaborate with various teams to ensure functional correctness and performance. This position offers the opportunity to solve complex technical problems in a dynamic and innovative environment.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience in high-performance ASIC design.
• Experience architecting or designing RTL solutions for digital systems.
• Experience developing networking IP across one or more layers, such as the media access control (MAC), link (L2), or physical (PHY) layers.
• Experience with high-speed interconnects.

• Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
• Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.
• Define and document the microarchitecture for complex digital designs within the TPU.
• Write high-quality, performant, and power-efficient RTL code, primarily in SystemVerilog.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.