The Low Power Verification Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration, particularly through the development of custom silicon solutions for Tensor Processing Units (TPUs). The engineer will be part of a team that drives innovation in AI and infrastructure, ensuring the successful implementation of low-power design methodologies. This position requires expertise in physical design verification and collaboration with various teams to enhance Google's AI capabilities. The role emphasizes the importance of validating complex designs and addressing technical challenges in low-power architecture.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 8 years of experience performing post-layout physical netlist validation and low-power signoff within advanced ASIC design workflows.
• Experience with static low-power rule-checking tools, including debugging structural checks and signal corruption issues.
• Experience validating special low-power components across all stages from synthesis to place and route.

• Design, deploy, and carry out post-layout low power verification methodologies according to execution schedules and tapeout signoff criteria.
• Validate the implementation of complex multi-voltage design collateral, performing gate-level checks using industry-standard tools.
• Drive the resolution of complex Physical Design and Place & Route anomalies, mitigating issues such as wrong domain buffering and secondary power routing failures.
• Perform debugging on advanced Clock Tree Synthesis implementations, analyzing tool behavior around level shifters in high fanout networks.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.