The Principal Engineer will lead Signal and Power Integrity development within AMD's Adaptive and Embedded Computing Group. This role focuses on driving SI/PI strategy and execution across various design levels for next-generation FPGA and adaptive computing products. The engineer will collaborate with multiple teams, define technical direction, and mentor junior engineers. The position requires a strong technical leader with expertise in Signal Integrity and Power Integrity fundamentals.

• MS or PhD in Electrical Engineering preferred
• Deep expertise in Signal Integrity with a working knowledge of Power Integrity concepts
• Hands-on experience performing lab measurements and correlating hardware results to simulation models
• Experience with DDR, LPDDR, HBM, or other high-performance memory interfaces
• Strong communication and cross-functional collaboration skills
• Experience mentoring engineers and driving technical leadership across organizations
• Experience with programming in Python, C++, and Matlab

• Responsible for technical solution development for Signal Integrity and Power Integrity.
• Drive system-level SI/PI architecture, design guidelines, and layout recommendations.
• Perform end-to-end channel simulations for high-speed serial interfaces and memory subsystems.
• Lead SI/PI analysis and optimization of DDR4, DDR5, LPDDR4, LPDDR5, HBM, and other high-performance memory interfaces.
• Correlate simulations with lab measurements and drive root-cause analysis of signal and power integrity issues.
• Collaborate with silicon, package, PCB, architecture, and manufacturing teams to resolve complex SI/PI challenges.
• Guide junior engineers on simulation methodologies, measurements, and debug techniques.
• Evaluate future package and PCB technologies to support next-generation FPGA and adaptive computing products.

• AMD provides a competitive 'Total Rewards' package that focuses on financial growth, health, and work-life balance.