The Design Verification Engineer role at Google focuses on ensuring the functionality and reliability of complex digital design blocks. The team combines expertise in AI, software, and hardware to create innovative technologies that enhance computing experiences. This position involves collaborating with design engineers to develop verification strategies and environments. The goal is to achieve coverage closure and ensure bug-free silicon in complex systems on chips (SoCs).

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience working with verification methodologies and languages, including SystemVerilog and UVM.
• Experience with interconnect protocols such as AXI, APB, and ACE.
• Experience building and maintaining verification test benches, test cases, and test environments.

• Plan verification strategies for complex digital design blocks by understanding design specifications.
• Build constrained-random verification environments utilizing SystemVerilog and Universal Verification Methodology (UVM).
• Define and implement comprehensive coverage metrics targeting stimulus and corner cases.
• Debug test failures alongside design engineers to ensure functionally correct design blocks.
• Achieve coverage closure to identify verification gaps and demonstrate progress toward tape-out.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.