This role is part of the Logic Design and Validation group within the Design Technology Platforms department, focusing on the development of RTL models and pre-silicon validation tests for next-generation semiconductor technology. The position involves collaboration with multidisciplinary teams to ensure high-quality silicon delivery. Candidates will engage in verification environments and strategies, as well as RTL development and integration. This is an opportunity to work at the forefront of chip design and validation.

• Master's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with a minimum of 1+ years of relevant experience, or a Bachelor's degree with a minimum of 3+ years of relevant experience.
• Experience with pre-silicon logic validation using SystemVerilog and UVM.
• Experience in digital design using Verilog and/or SystemVerilog.
• Hands-on experience with UVM testbench design, focusing on reusability and scalability.
• Scripting proficiency in Python, Perl, or TCL for design and verification automation.

• Design and develop verification environments by building and maintaining scalable, reusable UVM-based testbenches and test cases.
• Define and drive comprehensive verification plans for complex digital systems.
• Develop RTL designs and integrate logic components into SoC architectures.
• Create and apply SystemVerilog Assertions to improve verification quality.
• Identify, debug, and resolve pre-silicon failures while implementing corrective measures.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.