The Senior Static Timing Engineer will be part of a team focused on developing custom silicon solutions for Google's direct-to-consumer products. This role involves working on the physical implementation of ASICs using advanced technology nodes and ensuring timing closure for high-performance compute ASICs. The engineer will contribute to the development of static timing methodologies and automation scripts while collaborating with various teams to meet design requirements. This position is crucial for shaping the next generation of hardware experiences at Google.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with static timing analysis.
• Experience in Primetime or Tempus Tcl scripting and static timing analysis debug.
• Experience in full chip timing sign-off checklist criteria and overseeing final timing sign-off for ASICs.

• Perform full chip static timing analysis, timing ECO creation for timing convergence, and final timing sign-off for ASIC tape outs.
• Debug and resolve common STA or design rule issues like unconstrained endpoints, maximum transition, minimum period, or minimum pulse width violations.
• Develop timing constraints and verify them for sign-off.
• Utilize Perl, Python, Tcl, or Bash to create static timing flow automation scripts.
• Own and maintain Primetime STA flows.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.