The Silicon Engineer for Power Analysis at DeepMind will be part of a team focused on developing custom silicon solutions for Google's consumer products. This role involves working on ASIC power analysis and optimization, contributing to innovative hardware experiences. The engineer will collaborate with silicon foundries and external vendors to ensure successful tape-outs. The position emphasizes automation and integration of power analysis processes to enhance performance and efficiency.

• 7 years of experience working in ASIC power analysis and optimization, including experience with production chips.
• Experience in tape-outs of chips.
• Experience interacting and collaborating with silicon foundries and other external vendors for the tapeout process.
• Experience with Verilog and industry-standard EDA tools for power analysis and optimization design.
• Experience with scripting languages for automation of power analysis and optimization flows.
• Software development experience.

• Architect advanced technology node power solutions and establish use case budgets with block and full-chip estimations.
• Lead and drive the automation and integration of power analysis processes into our automated flow.
• Apply hardware expertise to build and integrate software components for automated power analysis and optimization.
• Partner with systems power and cross-functional teams to define and advocate for power management methodologies.
• Specify requirements for power management IPs while managing their design, integration, and post-silicon validation.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.