The Physical Design Engineer for 3D Technology at Google will focus on shaping the future of AI/ML hardware acceleration by driving the development of cutting-edge TPU technology. This role involves collaborating with various teams to develop new physical design methodologies and optimize ASICs and SoCs. The engineer will work on overcoming the challenges posed by Moore's Law while ensuring product success through innovative design solutions. The position is part of a team dedicated to redefining capabilities in AI and Infrastructure.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with physical design and 3D integration technologies, such as 3D-IC, 2.5D, chip stacking, vertical stacking, Integrity, or Through-Silicon Vias (TSV).
• Experience running industry standard tools for chip design, such as Synopsys, Cadence, Siemens EDA/Mentor Graphics.

• Drive development of a leading edge 3D technology platform for custom, high performance ASICs and SoCs, from design through manufacturing, packaging, and test.
• Optimize digital blocks for performance, power, area, and reliability using physical design and circuit techniques.
• Define optimal methodologies by investigating performance, power, and area across different technology nodes and implementation techniques.
• Work with our physical design, technology, circuits, and architecture teams plus IP partners in advanced CMOS nodes.
• Design and build custom circuits at the transistor and gate levels to support physical design and floorplan optimization.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.