The TPU RTL Design Engineer at Google Cloud will focus on shaping the future of AI/ML hardware acceleration by developing custom silicon solutions for Tensor Processing Units (TPUs). This role involves working on SoC-level RTL design for data center accelerators, with a specific emphasis on clock control subsystems and chassis infrastructure. The engineer will collaborate with various teams, including architecture, power, and design validation, to ensure the successful integration of complex digital designs. This position offers an opportunity to contribute to groundbreaking innovations that empower Google's AI/ML applications.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 2 years of experience in ASIC RTL design, focusing on clocking, reset, or timing-critical RTL development.
• Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL.
• Experience using Python, Tcl, or Perl for automating design tasks and data analysis.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.

• Create and review clock control subsystem's design micro-architecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Evaluate features and their impact in collaboration with architecture and power teams.
• Create test plans to verify and debug design RTL with Design Validation teams.
• Ensure design meets physical requirements and timing closure while working with physical design teams.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.