The Senior Mask Layout Design Engineer will join NVIDIA's dynamic team, focusing on high-speed mixed-signal circuit designs. This role involves working with a diverse group of engineers to customize designs for integration in VLSI products. The engineer will perform physical layout for various mixed-signal functions using advanced Cadence tools. The position requires a deep understanding of analog circuit layout concepts and experience with FinFET technology.

• Hold a BSEE or equivalent experience, with MSEE being a plus.
• Have 8+ years of relevant mask design/layout experience.
• Possess tape-out experience with FinFET technology, preferably with TSMC N5/N4/N3.
• Have experience with high-speed SerDes/RF layout design.
• Demonstrate validated experience with Cadence custom circuit design tools, particularly Virtuoso.
• Be proficient in scripting languages like Perl, Python, or Skill.
• Have knowledge of DRC and LVS checking flows and the ability to customize DRC and LVS decks.

• Perform physical layout for mixed-signal functions like PLL's and high-speed I/O circuits using Cadence tools.
• Collaborate with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
• Conduct floor planning, custom layout, and verification against design rules and schematics.
• Run and debug DRC and LVS with verification tools such as ICV/Calibre.
• Work optimally in a team, demonstrating good interpersonal skills and positive energy.

• Employees at NVIDIA are often offered comprehensive, day-one benefits—including medical, dental, and vision coverage with HSA support, life and disability insurance, an Employee Assistance Program, and a 401(k) with auto-enrollment. Many roles also have generous time off and holidays, donation matching (up to $10,000), and a wide menu of extras like FSAs, commuter benefits, legal and identity-theft protection, pet insurance, and wellness discounts. Optional programs can include student-loan and home-purchase support, plus family care resources and expert medical services.