As an IP Design Verification Engineer at Intel's Central Engineering Group, you will ensure the functional accuracy and reliability of clock generator IPs, such as PLL and FLL. You will develop verification environments, implement tests, and debug pre-silicon issues to meet rigorous specifications. This role is crucial for the seamless integration of IPs into Intel's innovative designs. Join a team dedicated to enhancing engineering methodologies and supporting Intel's industry leadership.

• Bachelor's Degree in Electrical or Computer Engineering or a related field with 4+ years of relevant experience, or a Master's Degree with 3+ years, or a PhD with 1+ year of relevant experience.
• 2+ years of experience in design verification and validation methodologies, including UVM, System Verilog, and industry-standard EDA tools.
• 2+ years of experience with scripting languages such as Python and Perl.

• Develop test benches, verification environments, and tests using System Verilog and UVM to ensure comprehensive IP validation.
• Perform functional verification for clock generator IPs such as PLL and FLL, ensuring conformance to microarchitecture specifications.
• Maintain and refine verification infrastructure and methodologies for multiple IP generations.
• Debug and root-cause pre-silicon issues within the verification environment.
• Document test plans and participate in technical reviews with design teams.
• Collaborate cross-functionally with architects, RTL developers, and analog design teams to enhance verification of architectural and microarchitectural features.
• Lead Mixed Signal Validation activities, including AMS simulations, schematic debugging, and resolving cross-functional issues.
• Contribute to the definition and refinement of architectural and microarchitectural features for IP design.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.