The Senior ASIC Physical Design Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration through the development of custom silicon solutions. This position involves collaboration with various teams to drive cutting-edge TPU technology that powers Google's demanding applications. The engineer will leverage their expertise in physical design to solve complex technical problems while optimizing performance, power, and area. The role is part of a team that is redefining capabilities in AI and Infrastructure, delivering unparalleled computing power and insights.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 7 years of experience with physical design from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure.
• Experience in Python, Tcl, or Perl scripting.
• Experience working with external partners on physical design closure.
• Experience in static timing analysis with an understanding of timing corners, margins, and derates.
• Experience with Synopsys/Cadence PnR tools.
• Understanding of DFT including Scan, MBIST, and LBIST.
• Understanding of performance, power, and area trade-offs.

• Participate in the physical design of complex blocks.
• Contribute to the design and closure of the full chip and individual blocks from RTL to GDS.
• Collaborate with internal logic and internal and external teams to achieve optimal power/performance analysis.
• Conduct feasibility studies for new microarchitectures and optimize runs for finished RTL.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.