The RTL Design Engineer position at Google focuses on developing custom silicon solutions that enhance Google's direct-to-consumer products. The role involves working within a team that combines AI, software, and hardware to create innovative technologies. The engineer will contribute to shaping the next generation of hardware experiences, ensuring high performance and efficiency. This position requires collaboration and expertise in ASIC development and design methodologies.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with IP development or integration.
• Experience in ASIC development with Verilog or VHDL.
• Experience with a scripting language like Perl or Python.

• Define microarchitecture for a subsystem.
• Integrate internal or external IP.
• Define microarchitecture of a small to medium size IP.
• Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
• Participate in test plan and coverage analysis of the sub-system and chip-level verification.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.