The Senior Staff CPU Cache Subsystem Design Engineer will be part of a team that develops custom silicon solutions for Google's products. This role focuses on leading a front-end design team and collaborating with various cross-functional teams to define microarchitecture and deliver high-quality RTL. The engineer will also be responsible for evaluating design options based on complexity, performance, power, and area. This position offers the opportunity to shape the next generation of hardware experiences that enhance user interactions with technology.

• Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.
• 15 years of experience in high-performance CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches.
• Experience leading technical teams for modern processor subsystems with high speed and lower power design.
• Experience with front-end quality checks such as Lint and CDC/RDC.

• Lead a team of digital design engineers working on CPU functional units, focusing on microarchitecture and RTL design.
• Review and propose performance-enhancing microarchitecture features while collaborating with software, architecture, and performance teams.
• Deliver comprehensive plans to achieve project milestones and execution goals.
• Collaborate with verification, physical design, and power analysis teams to ensure designs meet frequency, power, and area targets.
• Direct load-store unit and cache subsystem design optimizations across CPU components.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.