The SoC DFT Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration through the development of advanced design-for-test methodologies for SoCs. You will work within a team dedicated to pushing the boundaries of custom silicon solutions, specifically targeting TPU technology. This position involves collaborating with the Silicon Engineering team to enhance production quality and reduce test costs. Your expertise will contribute to the innovation behind products that impact millions of users worldwide.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience in DFT architecture, implementation, and verification for SoCs.
• Experience in silicon bring-up, debug, or validation of DFT features.
• Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).

• Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG.
• Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality.
• Develop diagnostic databases, software and hardware for logic and memory fail debug.
• Design and implement system level test strategy.
• Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT compression, Logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.