The Staff ASIC Power Engineer for ML Accelerators at Google will focus on shaping the future of AI/ML hardware acceleration, particularly through the development of Tensor Processing Units (TPUs). This role involves driving power efficiency for TPU designs and contributing to innovative custom silicon solutions. The engineer will work within a team dedicated to improving power modeling and optimization techniques, ensuring that Google's AI applications operate at peak efficiency. The position requires collaboration with cross-functional teams to create novel power management architectures.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in design or architecture, including logic design, power architecture, performance, or SoC design.
• Experience with power design, power modeling, power architecture, or power reduction methodologies.

• Contribute to design power modeling and drive convergence to power targets.
• Investigate, spec, and deploy architectural and microarchitectural power optimization techniques.
• Define best practices and methodologies to achieve low-power RTL designs.
• Collaborate with cross-functional software and system teams to create novel power management architectures to meet dynamic power targets.
• Own the execution and delivery of complex technical projects end-to-end while being the technical lead of an experienced power team.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.