As a Senior ASIC Design Engineer at Qualcomm, you will be part of the Next Generation, High-Speed, Memory and Cache Controller Design Team. Your primary focus will be on the architecture, design, and deployment of high-speed memory systems, specifically for HBM/LPDDR/DDR memory controllers. You will work closely with cross-functional teams to ensure high performance and low power designs. This role requires a strong background in digital and/or analog design, as well as experience with various memory architectures.

• Bachelor's or Master's degree in Science, Engineering, or a related field.
• 3+ years of experience in ASIC design or related areas.
• Experience with LPDDR memory and cache controller design.
• Familiarity with NoC based architectures and front-end interfacing to CPUs, DSPs, and multimedia processors.
• Exposure to HBM memory type designs.

• Define, model, design, optimize, verify, validate, implement, and document IP development.
• Develop architecture and design specifications for high-speed memory systems.
• Implement and deliver RTL designs while collaborating with verification engineers.
• Debug designs and provide support during integration into the chip.
• Contribute to the improvement of design methodology to enhance productivity and quality.

• Qualcomm offers competitive compensation, annual bonuses, stock programs, comprehensive healthcare coverage, retirement plans, wellness programs, parental leave, flexible work options, and professional development opportunities.